C4 arrays are conventionally tested with probe devices. The probe devices have multiple probe tips that respectively make electrical contact with the ball structures (or, more generically, input/output (I/O) pads of the C4 array). Each probe tip of the probe is mutually electrically isolated so that power or signals conducted to one tip will not affect readings from the other tips. The I/O pads of a semiconductor die are usually arranged as an array, such as an array of one of the following types: (i) regular rectangular array; and (ii) staggered array (see Definition, below). As will be appreciated from the definition of “staggered array”, in a staggered array (i) the objects of alternating columns have objects in the same aligned rows of the staggered array, but (ii) the objects of adjacent column are offset from each other into different rows of the staggered array.
It is known that the I/O pads of an array are respectively characterized by different I/O pad types, such as power supply pad, ground pad, and data signal pad. For a given die: (i) power supply type pads may have different respective power levels (for example, C1 level and V2 level); and (ii) data signal type pads will generally each have a different particular data signal. Generally, each I/O pad that is contacted by a probe tip will only be contacted by one probe tip. It is known that a single probe tip cannot, without risk of damage and/or bad test data, touch both of the following at the same time: (i) a pad having a first data signal; and (ii) a pad of any other type or a pad having a data signal other than the first data signal. Because of this important restriction, conventional probe tips are structured and controlled to touch no more than one pad at the same time, and are carefully controlled in operation to touch no more than one pad at a time. Advances in wafer testing of high pin count chips includes: (i) the reduced pin count test, where only a subset of so-called test pins, or data signal type pads, are required to be connected during the wafer test application. The design for testing the chip addresses the high I/O pad coverage by not contacting all data signal type pads.
The probe devices used in wafer testing, also referred to as beta testing, and subsequent integrated circuit (IC) testing are generally configured as probe cards containing multiple microscopic probes. It is the alignment of these microscopic probes (that is, the registration between the I/O contact pads on the wafer and the probe tips) that ensures contact with the correct I/O pad types as the pads and the tips are relatively moved into an electrically connecting (that is, contacting) position.
It is understood that potential testing problems include the following: (i) losing electrical contact with the high density C4, or flip chip; (ii) electrical shorting, by a probe tip, between two data signal pads that have different data signal; and/or (iii) electrical shorting, by a probe tip, between a data signal pad and another pad that is of the ground type or the power type.